MAX1285BESA+T【PDF 2/15 页】IC ADC 12BIT 300KSPS 8-SOIC

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MAX1284/MAX1285

400ksps/300ksps, Single-Supply, Low-Power,

Serial 12-Bit ADCs with Internal Reference

______________________________________________________________________________________

Figure 5. Supply Current vs. Conversion Rate

To start a conversion, pull CS low. At CS’s falling edge,

the T/H enters its hold mode and a conversion is initiat-

ed. Data can then be shifted out serially with the exter-

nal clock.

Using SHDN to Reduce Supply Current

Power consumption can be reduced significantly by

shutting down the MAX1284/MAX1285 between con-

versions. Figure 5 shows a plot of average supply cur-

rent versus conversion rate. The wake-up time (tWAKE)

is the time from when SHDN is deasserted to the time

when a conversion may be initiated (Figure 6). This

time depends on the time in shutdown (Figure 7)

because the external 4.7F reference bypass capacitor

loses charge slowly during shutdown and can be as

long as 2ms.

Timing and Control

Conversion-start and data-read operations are con-

trolled by the CS and SCLK digital inputs. The timing dia-

grams of Figures 8 and 9 outline serial-interface

operation.

A CS falling edge initiates a conversion sequence: the

T/H stage holds the input voltage, the ADC begins to

convert, and DOUT changes from high impedance to

logic low. SCLK is used to drive the conversion

process, and it shifts data out as each bit of conversion

is determined.

SCLK begins shifting out the data after the rising edge

of the third SCLK pulse. DOUT transitions 20ns after

each SCLK rising edge. The third rising clock edge

produces the MSB of the conversion at DOUT, followed

by the remaining bits. Since there are twelve data bits

and three leading zeros, at least fifteen rising clock

edges are needed to shift out these bits. Extra clock

pulses occurring after the conversion result has been

clocked out, and prior to a rising edge of CS, produce

trailing zeros at DOUT and have no effect on converter

operation.

Pull CS high after reading the conversion’s LSB. For

maximum throughout, CS can be pulled low again to

initiate the next conversion immediately after the speci-

fied minimum time (tCS).

Output Coding and Transfer Function

The data output from the MAX1284/MAX1285 is binary,

and Figure 10 depicts the nominal transfer function.

Code transitions occur halfway between successive-

integer LSB value VREF = +2.5V, and 1LSB = 610V or

2.5V/4096.

COMPLETE CONVERSION SEQUENCE

CONVERSION 0

CONVERSION 1

POWERED-UP

POWERED-DOWN

tWAKE

DOUT

SHDN

Figure 6. Shutdown Sequence

0.1

100

10k

0.1

100

1000 10,000 100,000

CONVERSION RATE (ksps)

SUPPLY

CURRENT

(μ

VDD = 3V

DOUT = FS

RL =

∞

CL = 10pF

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